Dynamic devices are synchronous logic circuits that generate an output depending upon a predetermined combination of inputs for performing a logical function. Dynamic devices are characterized by two states, precharge and evaluate. In the precharge state, a precharge (or storage) node is charged to a known or predetermined voltage level. In the evaluate state, a logic section (or xe2x80x9ctreexe2x80x9d) of pull-down transistors configured to perform a basic logical function (e.g., NAND, NOR, or combination thereof) is given the opportunity to discharge the node to a second known or predetermined voltage level or to allow the charge to persist.
The logic section is typically connected between the precharge node and a controllable virtual ground (or DNG) node. In turn, the logical function input signals are connected to the gates of one or more of the transistors in the logic section tree for activating the logic section and xe2x80x9csinkingxe2x80x9d the charge at the precharge node through the DNG node if the logical function inputs satisfy the particular logical function being implemented. A transistor (commonly referred to as a DNG transistor) is typically connected between the DNG node and ground, and a precharge transistor is connected between the precharge node and a supply voltage. During a precharge state (when the logical inputs are not valid), the DNG transistor is turned off, and the precharge transistor is turned on so that the precharge node charges regardless of whether the logic section conducts between the precharge and DNG nodes. On the other hand, during an evaluate state, the DNG transistor turns on, and the precharge transistor turns off, thereby allowing the logic section to discharge the precharge node if so dictated by the logical function inputs.
Dynamic circuits are typically implemented with field effect transistors (xe2x80x9cFETxe2x80x9ds) including both P-type (xe2x80x9cPFETxe2x80x9d) and N-type (xe2x80x9cNFETxe2x80x9d) transistors. For example, in one common parallel NOR configuration, a PFET transistor, with its gate connected to a clock signal, is used as the precharge transistor; an NFET transistor, with the clock signal also connected to its gate input, is used as the DNG transistor; and two or more parallel NFET transistors connected between the precharge and DNG nodes, with the logical inputs connected to their gate inputs, are used as the pull-down transistors forming the logic section. In this configuration, when the clock signal is low (precharge state), the NFET DNG transistor turns off, and the precharge PFET transistor turns on to charge the precharge node. Conversely, when the clock signal is high (evaluate state), the precharge PFET transistor turns off, and the DNG NFET transistor turns on to discharge the precharge node if the logic section is activated by the logical function inputs.
With reference to FIG. 1, a non-idealized equivalent circuit 100B is shown for a conventional FET transistor 100A (which happens to be an NFET transistor Q1). The equivalent circuit 100B comprises a parasitic bipolar junction transistor (xe2x80x9cBJTxe2x80x9d) portion Q1B connected in parallel across a FET portion Q1A. As is depicted in the equivalent circuit 100B, the FET Q1 has an associated drain leakage current, IL, which has components from both the FET portion Q1A and the parasitic bipolar portion Q1B. It also has a xe2x80x9cbody,xe2x80x9d which corresponds to the base of the parasitic BJT In circuit analysis and design, the body is normally not considered because with most FET manufacturing processes, it is connected to either the supply voltage or ground, which effectively eliminates its influence on the FET. However, with partially depleted silicon-on-insulator (xe2x80x9cSOIxe2x80x9d) processes, the body is left to float between the drain and the source. This leads to several adverse effects when such FETs are used in dynamic circuits. First, it decreases the pull-down transistors"" input threshold levels, which increases their leakage currents attributable to their equivalent FET portions. Second, during the evaluate state it allows the equivalent parasitic bipolar portions to be activated, which increases their leakage currents at this critical time.
A FET transistor has an associated input threshold voltage, VT, that determines the required input voltage, VGS, for turning it on. Thus, for example, with an NFET transistor, if its input voltage (VGS) is greater than the input threshold voltage level (VT), then the FET is said to bexe2x80x9cturned on.xe2x80x9d However, even when VGS is less than VT, there is still a finite amount of drain current, which is referred to as sub-threshold leakage current. This sub-threshold leakage current, which is part of the FET""s overall leakage current, IL, increases as VGSxe2x88x92VT increases. In fact, in the subthreshold region the amount of drain current, ID, that can flow through the FET is exponentially proportional to the input voltage, VGS. Unfortunately, one physical characteristic of FET transistors is that their input threshold voltages are inversely proportional to their body voltages. For example, with NFET transistors, as their body voltages increase, their input threshold levels decrease. Thus, with partially depleted SOI NFETs whose body voltages are allowed to float upward, their input threshold voltages are lowered, which exponentially increases their leakage currents due to the ambient electrical noise at their gate inputs. When such FETs are used as pull-down transistors in dynamic circuits, this increased leakage current causes them to be more susceptible to wrongfully discharging the precharge node.
The upwardly floating body voltages impose even greater problems as a result of the parasitic BJT portions. During the precharge state, the DNG node is normally charged to a level that is approximately an input threshold voltage, VT, lower than the voltage at the precharge node. This means that the body voltage will be somewhere between these two relatively high voltages. However, when the circuit evaluates, and the DNG node discharges to ground, a significant voltage drop is then induced between the body and the DNG node, which corresponds to the emitter of the parasitic bipolar transistor Q1B. This forwardly biases the bipolar transistor thereby producing xe2x80x9ccollectorxe2x80x9d current, which adds to the overall FET leakage current, IL. Thus, the leakage current in the logic section is significantly increased during the evaluate state, which can cause the circuit to wrongfully evaluate to a discharged level even though the logic section is not suppose to be activated based on the logical input values.
Several different solutions have been used to address this problem. With one solution, an NFET transistor with an inverted clock input is connected across the DNG transistor to bleed away the charge at the DNG node during the precharge state and thereby lower the body voltages of the pull-down transistors. This xe2x80x9cbleed-offxe2x80x9d transistor is sized large enough to sufficiently discharge the DNG node yet small enough to ensure that the precharge node properly charges during the precharge state. Unfortunately, this solution is disfavored because it requires three extra transistorsxe2x80x94one transistor for discharging the DNG node and two transistors for providing an inverted clock input.
Another solution incorporates the use of an over-sized holder transistor. A holder transistor is typically used in a dynamic circuit to supply additional charge to the precharge node for xe2x80x9choldingxe2x80x9d it charged -even when the pull-down transistors leak charge through to the DNG node. This solution simply involves using an over-sized holder transistor for compensating against the increased pull-down transistor leakage currents caused by their increased body voltages. Unfortunately, this solution is also disfavored because it excessively slows down the circuit""s ability to precharge and evaluate, which impairs its ability to operate at high-performance frequencies.
The present invention is directed to a system and method for dynamic circuits. In one embodiment, the circuit includes a precharge device, a DNG FET transistor, and at least one pull-down FET transistor with a floating body. The precharge device is connected to a precharge node for charging it during a precharge state. The DNG FET transistor is connected between a DNG node and a charge sink for operably linking the DNG node to the charge sink during an evaluate state. In addition, the DNG transistor has an associated precharge leakage current. The at least one pull-down FET transistor has an input threshold voltage whose value is inversely affected by its floating body voltage. The at least one pull-down transistor is connected between the precharge node and the DNG node for discharging the precharge node during the evaluate state if so dictated by logical function input values applied to the pull-down transistors during the evaluate state. The DNG leakage current, during the precharge state, draws a sufficient amount of charge from the DNG node to maintain the at least one pull-down transistor body voltage(s) at a sufficiently low value so that the precharge node does not wrongfully evaluate to a discharge level during the evaluate state.